Method, system, and computer program product for schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designs

ABSTRACT

Disclosed are methods and systems for by identifying or generating an electrical schematic, generating a thermal schematic by associating thermal RC circuits of the electronic design with the electrical schematic, performing at least two analyses of an electrical analysis, a thermal analysis, and an electromagnetic interference compliance (EMC) analysis with the electrical schematic and the thermal schematic of the electronic design. The electrical, thermal, and EMC analyses may be performed concurrently by forwarding intermediate or final analysis results to each other, and the analysis results may be presented simultaneously in one or more user interface windows. The thermal schematic may be obtained by extracting the thermal RC circuits, identifying corresponding electrical circuit components that correspond to the extracted thermal RC circuits, and importing the thermal RC circuits into the electrical schematic so that the electrical and thermal schematics have the same nodes.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is related to U.S. patent application Ser. No.14/224,047 entitled “METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FORIMPLEMENTING THERMAL CIRCUIT EXTRACTION FOR TRANSIENT THERMAL ANALYSESFOR ELECTRONIC CIRCUIT DESIGNS” and filed on Mar. 24, 2014 under Atty.Dkt. No. 14PA007US01 and U.S. Pat. No. 7,490,309 entitled “Method andsystem for automatically optimizing physical implementation of anelectronic circuit responsive to simulation analysis” and filed on Aug.31, 2006 under U.S. patent application Ser. No. 11/513,061. The contentof the aforementioned U.S. patent application and U.S. patent is herebyexpressly incorporated by reference in its entirety for all purposes.

BACKGROUND

As VLSI technology scales, interconnects are becoming the dominantfactor determining system performance and power dissipation.Interconnect reliability due to electro-migration and electromagneticinterference compliance (EMC) are fast becoming serious design issuesparticularly for long signal lines. In fact, it has been recently shownthat interconnect Joule heating in advanced technology nodes canstrongly impact the magnitude of the maximum temperature of the globallines despite negligible changes in chip power density which will, inturn, strongly affect the electro-migration lifetime of theinterconnect. In analog designs, uni-directional current flow andsmaller wire geometries create EM concerns for the signal nets as well.The behavior of analog circuits is even more sensitive to layout inducedparasitics and thus electro-migration problems due to the unidirectionalcurrent flows in various circuit components. Parasitics not onlyinfluence the circuit performance but may often render itnon-functional.

In addition to the rising concerns about electro-migration, voltagedrop, also called IR drop, represents another class of challenges formodern electronic circuits. Voltage drop represents the voltagereduction that occurs on power supply networks. The IR drop may bestatic or dynamic and results from the existence of non-idealelements—the resistance within the power and ground supply wiring andthe capacitance between them. While static voltage drop considers onlythe average currents, dynamic voltage drop considers current waveformswithin clock cycles and has an RC transient behavior. Similar effectsmay be found in ground wiring, usually referred as ground bounce,whereby current flows back to the ground/V_(SS) pins causing its voltageto fluctuate. Both effects contribute to lower operating voltages withindevices (e.g., logic cells/gates in digital circuits), which in generalincreases the overall time response of a device and might causeoperational failures due to heat dissipation.

Conventional steady-state or transient thermal analyses use timeconsuming time-stepping or domain discretization algorithms such asfinite element methods or finite difference methods on discretizeddesigns. Moreover, these conventional steady-state or transient thermalanalyses are often after-the-fact in that these analyses are usuallyperformed after electronic designs are completed at, for example, theblock level, the chip level, the package level, or even the board levelat which integrated circuit blocks are integrated with a printed circuitboard. The limitations on the sizes of time-step and the amount ofcomputation time as well as intensive computation have renderedtransient thermal analyses less than desired. Moreover, conventional EMCanalyses are often performed as separate analyses detached from theelectronic design stage and the thermal analyses of the electronicdesigns.

Given the advantages provided by the thermal analyses, EMC analyses, andthe electrical analyses, there exists a need for effective and efficienttechnique to implement schematic driven, unified thermal andelectromagnetic interference compliance analyses for electronic circuitdesigns.

SUMMARY

Disclosed are method(s), system(s), and article(s) of manufacture forschematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in one or moreembodiments. Some embodiments are directed at a method for schematicdriven, unified thermal and electromagnetic interference complianceanalyses for electronic circuit designs. The method identify or generatea representation of an electronic design, generate a thermalrepresentation of the electronic design by associating thermal RCcircuits of the electronic design with the representation, and performat least two analyses of an electrical analysis, a thermal analysis, andan electromagnetic interference compliance (EMC) analysis with therepresentation and the thermal representation of the electronic designin some embodiments described below.

In some of these embodiments, the method may further extract the thermalRC circuits for the electronic design, wherein the representationcomprises an electrical schematic of the electronic design, and thethermal representation comprises a thermal schematic including samenodes as the electrical schematic. In addition or in the alternative,the method may further identify the thermal RC circuits of theelectronic design, identify corresponding electrical circuit componentsthat correspond to the thermal RC circuits in the representation of theelectronic design, and forming the thermal representation by at leastimporting the thermal RC circuits into the representation according tothe corresponding electrical circuit components in the representation ingenerating the thermal representation.

In some embodiments, the method may perform at least one of associatingone or more electrical characteristics and/or one or more physicalcharacteristics with the representation and/or the thermalrepresentation of the electronic design; stitching the one or moreelectrical characteristics and/or the one or more physicalcharacteristics into the representation and/or the thermalrepresentation of the electronic design; and annotating one or moreelectrical characteristics and/or one or more physical characteristicsonto the representation and/or the thermal representation of theelectronic design. Moreover, the thermal analysis may be performed byusing at least one general purpose circuit simulator including a SPICE(Simulation Program with Integrated Circuit Emphasis) or SPICE-likesimulation engine in some embodiments, instead of or rather than usingtime-stepping or domain discretization numerical techniques such asvarious finite element methods and finite difference methods.

In some embodiments, the method may determine steady-state thermalresponses of the electronic design by using the results and/or determinetransient thermal responses of the electronic design by using theresults. Additionally or alternatively, the method may forward thermalanalysis results to the electrical analysis or the EMC analysis andperform the electrical analysis or the EMC analysis with at least thethermal analysis results to obtain electrical analysis results or EMCanalysis results in some embodiments. In some of the immediatelypreceding embodiments, the method may further forward the electricalanalysis results or the EMC analysis results to the thermal analysis andperform the thermal analysis with at least the electrical analysisresults or the EMC analysis results to obtain updated thermal analysisresults until a criterion is satisfied.

Moreover, the method may perform an electrical simulation on therepresentation of the electronic design to obtain one or more electricalcharacteristics of the electronic design, wherein the one or moreelectrical characteristics include one or more pin currents and powerdissipation of one or more devices in some embodiments. Based at leastin part upon the results of at least two of the thermal analysis, theelectrical analysis, and the EMC analysis, the method may further modifyone or more first characteristics of the thermal representation of theelectronic design based at least in part upon the results andautomatically modify one or more second characteristics of therepresentation or a layout portion of the electronic design according tothe one or more first characteristics that are modified in someembodiments. In some of the preceding embodiments, the method mayfurther modify the one or more second characteristics of therepresentation or the layout portion of the electronic design based atleast in part upon the results and automatically modify the one or morefirst characteristics of the thermal representation of the electronicdesign according to the one or more second characteristics that aremodified.

In at least some of these embodiments, the one or more firstcharacteristics may include at least a size of a circuit componentdesign, and the one or more second characteristics include at least athermal resistance of the circuit component design. In some of the aboveembodiments, the electronic design may be at a pre-layout stage havingno placement or routing design information. In some other embodiments,the electronic design may be at a post-layout stage and include partialor complete placement design data or even partial or complete routingdesign data. The method may also optionally perform at least one ofidentifying electrical characteristics from the representation of theelectronic design and forwarding the electrical characteristics to thethermal representation of the electronic design for the thermalanalysis; sub-dividing a circuit component design into multiplesub-component designs and performing the at least two analyses with themultiple sub-component designs; and identifying one or more EMC criticalcomponents in the electronic design based at least in part upon theresults.

Some embodiments are directed at a hardware module or system that may beinvoked to perform any of the methods, processes, or sub-processesdisclosed herein. The hardware system may include one or more variantsof general purpose electronic circuit simulators include SPICE(Simulation Program with Integrated Circuit Emphasis) or SPICE-likesimulation engines, integration modules, model order reduction modules,various transforms, various matrix decomposition modules, various matrixfactorization modules, or one or more numerical modules, etc. in someembodiments. Each of these hardware modules may function by itself or inconjunction with other parts (e.g., the computer buses, communicationchannels or ports, non-transitory memory, processor(s) or processorcore(s), etc.) of a computing system. The hardware system may furtherinclude one or more forms of non-transitory machine-readable storagemedia or devices to temporarily or persistently store various types ofdata or information such as the firmware. Some illustrative modules orcomponents of the hardware system may be found in the SystemArchitecture Overview section below.

Some embodiments are directed at an article of manufacture that includesa non-transitory machine-accessible storage medium having storedthereupon a sequence of instructions which, when executed by at leastone processor or at least one processor core, causes the at least oneprocessor or the at least one processor core to perform any of themethods, processes, or sub-processes disclosed herein. Some illustrativeforms of the non-transitory machine-readable storage media may also befound in the System Architecture Overview section below.

More details of various aspects of the methods, systems, or articles ofmanufacture for implementing thermal circuit extraction for transientthermal analyses are described below with reference to FIGS. 1-14.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate the design and utility of various embodiments ofthe invention. It should be noted that the figures are not drawn toscale and that elements of similar structures or functions arerepresented by like reference numerals throughout the figures. In orderto better appreciate how to obtain the above-recited and otheradvantages and objects of various embodiments of the invention, a moredetailed description of the present inventions briefly described abovewill be rendered by reference to specific embodiments thereof, which areillustrated in the accompanying drawings. Understanding that thesedrawings depict only typical embodiments of the invention and are nottherefore to be considered limiting of its scope, the invention will bedescribed and explained with additional specificity and detail throughthe use of the accompanying drawings in which:

FIG. 1 illustrate a illustrative high level schematic block diagrams fora system for schematic driven, unified thermal and electromagneticinterference compliance analyses for electronic circuit designs in someembodiments.

FIG. 2A illustrates a high-level block diagram of a method or system forschematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.

FIG. 2B illustrates a schematic flow diagram for data flows betweenanalysis modules for schematic driven, unified thermal andelectromagnetic interference compliance analyses for electronic circuitdesigns in some embodiments.

FIG. 2C illustrates a more detailed block diagram for method or systemfor schematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.

FIG. 2D shows some illustrative exchange of data for concurrent crossdomain analyses in some embodiments.

FIG. 3 illustrates a high-level block diagram for a method or system forschematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.

FIG. 3A illustrates a more detailed block diagram for a method or systemfor schematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.

FIG. 3B illustrates another more detailed block diagram for a method orsystem for schematic driven, unified thermal and electromagneticinterference compliance analyses for electronic circuit designs in someembodiments.

FIG. 4 illustrates a high level block diagram for a process or modulefor performing schematic driven thermal analyses accounting for deviceheat dissipation and interconnect Joule heating for electronic circuitdesigns in some embodiments.

FIG. 5 illustrates a high level block diagram for a process or modulefor performing schematic driven thermal analyses accounting for deviceheat dissipation and interconnect Joule heating for electronic circuitdesigns in some embodiments.

FIG. 6 illustrates a portion of a user interface for the schematicdriven concurrent EMC, thermal, and electrical simulations techniquesdescribed above in some embodiments.

FIG. 7 shows a portion of a user interface illustrating a functional orelectrical simulation view for a method or system for schematic driven,unified thermal and electromagnetic interference compliance analyses forelectronic circuit designs in some embodiments.

FIG. 8 shows a portion of a thermal schematic view and a portion of anelectrical schematic view of an electron circuit design in someembodiments.

FIG. 9 illustrates a portion of a user interface for performing athermal simulation or analysis for an electronic circuit in someembodiments.

FIG. 10 illustrates tabulated electrical-thermal-EMC co-simulationresults including graphical indications of criticality of components ofan electronic design with respect to electromagnetic interferencecompliance in some embodiments.

FIG. 11 illustrates a portion of a user interface including a thermalschematic view and the corresponding placement layout of an electroniccircuit design or a portion thereof for cross-editing in someembodiments.

FIG. 12 illustrates a layout view or a portion thereof including analog,digital, mixed-signal components, and interconnects with associated orstitched schematic level electrical characteristics in some embodiments.

FIG. 13 illustrates an electric schematic view or a portion thereofincluding associated, stitched, or annotated electrical and thermal datafrom layout-based analyses in some embodiments.

FIG. 14 illustrates a computerized system on which a method forimplementing a physical design of an electronic circuit with automaticsnapping can be implemented.

DETAILED DESCRIPTION

Various embodiments of the invention are directed to a methods, systems,and articles of manufacture for method or system for schematic driven,unified thermal and electromagnetic interference compliance analyses forelectronic circuit designs. Other objects, features, and advantages ofthe invention are described in the detailed description, figures, andclaims.

Various embodiments will now be described in detail with reference tothe drawings, which are provided as illustrative examples of theinvention so as to enable those skilled in the art to practice variousembodiments described herein. Notably, the figures and the examplesbelow are not meant to limit the scope of the present invention. Wherecertain elements may be partially or fully implemented using knowncomponents (or methods or processes), only those portions of such knowncomponents (or methods or processes) that are necessary for anunderstanding of various embodiments will be described, and the detaileddescriptions of other portions of such known components (or methods orprocesses) will be omitted so as not to obscure the invention. Further,various embodiments encompass present and future known equivalents tothe components referred to herein by way of illustration.

Disclosed are method(s), system(s), and article(s) of manufacture formethod or system for schematic driven, unified thermal andelectromagnetic interference compliance analyses for electronic circuitdesigns in one or more embodiments.

FIG. 1 illustrate a illustrative high level schematic block diagrams fora implementing thermal circuit extraction for transient thermal analysesin some embodiments. In one or more embodiments, the system for FIG. 1illustrate a illustrative high level schematic block diagrams forimplementing thermal circuit extraction for transient thermal analysesmay comprise one or more computing systems 100, such as a generalpurpose computer described in the System Architecture Overview sectionto implement one or more special proposes.

In some embodiments, the one or more computing systems 100 may invokevarious system resources such as the processor(s) or processor core(s),memory, disks, etc. The one or more computing systems 100 may alsoinitiate or interact with other computing systems to access variousresources 128 that may comprise a global routing engine and/or a detailrouting engine 114, a layout editor 116, a design rule checker 118, averification engine 120, etc. The one or more computing systems 100 mayfurther write to and read from a local or remote volatile ornon-volatile computer accessible storage 112 that stores thereupon dataor information such as, but not limited to, one or more databases (124)such as schematic design database(s) or physical design database(s),various data, rule decks, constraints, etc. (122), or other informationor data (126) that may be used to facilitate the performance of variousfunctions to achieve the intended purposes.

In some embodiments, the one or more computing systems 100 may, eitherdirectly or indirectly through various resources 128 to invoke varioussoftware, hardware modules or combinations thereof 152 that maycomprises one or more simulators 102 (e.g., one or more variants ofSPICE—Simulation Program with Integrated Circuit Emphasis—simulators) toperform divide-and-conquer simulations, one or more library modules 104including numerical sub-routines, electrical, physical, and/thermalproperties, etc. to support the one or more simulators or one or moreother numerical computation modules, one or more numerical modules 106(e.g., a numerical module for performing convolution, a numerical modulefor performing numerical integration, a numerical module for performingmatrix decomposition, etc.) to perform various numerical tasks, one ormore model order reduction modules 108 (e.g., a Lanczos module forperforming Lanczos algorithm, an Arnoldi's algorithm for performing theArnoldi's algorithm, the Householder module for performing theHouseholder algorithm, an iterative numerical algorithm for determiningeigenvalues and eigenvectors of a matrix, etc.), one or more transformsor other numerical computation modules 110, or one or more EMC analysismodules, etc.

FIG. 2A illustrates a high-level block diagram of a method or system forschematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.In these embodiments illustrated in FIG. 2A, the method or system mayidentify (if existing) or generate (if non-existing) a representation ofan electronic circuit design by capturing a function view of theelectronic circuit at 202. In some of these embodiments, therepresentation of the electronic circuit design includes an electricalschematic design of the functional view which may further includes thefunctional description of the electronic circuit design or a portionthereof. The electronic circuit may include an integrated circuit (IC)design, an IC packaging design including an IC design, a PCB (printedcircuit board) design including one or more IC packaging designs, and atest bench design including the PCB design.

At 204, the thermal RC circuits of the electronic circuit design may beextracted for the electronic circuit design. In some of theseillustrated embodiments, electrical parasitics and/or physicalcharacteristics of one or more components may also be extracted ordetermined at 204, if a physical representation (e.g., a floorplan, aplacement layout, etc.) of the electronic circuit design is available.More details about thermal RC circuit extraction are described in U.S.patent application Ser. No. 14/224,047, the content of which is herebyexpressly incorporated by reference in its entirety for all purposes.

In some embodiments, the method or system may generate a thermalrepresentation of the electronic circuit by stitching the thermal RCcircuit network, associating the thermal RC circuit network with,importing the thermal RC circuit network into the representation,replacing corresponding circuit components in the representation withthe thermal RC circuit network, or by annotating the thermal RC circuitnetwork onto the representation of the electronic circuit design at 206.In some of these embodiments, the thermal representation of theelectronic circuit design includes a thermal schematic having the samenodes as the electrical schematic of the electronic design. In someembodiments, the association, stitching, importation, replacement, orannotation (hereinafter “association”, “associating”, or “importing”collectively) of thermal RC circuit network may be achieved by replacingthe electrical resistance (R_(E)) values, the electrical capacitance(C_(E)) values, and the current sources in the electrical schematic withthe corresponding thermal resistance (R_(TH)), the thermal capacitance(C_(TH)), and the power or current sources (P) representing powerdissipations of devices, respectively.

At 208, the method or system may further optionally associate electricalparasitics and/or physical characteristics that have been optionallyextracted or determined at 204 with the representation. In someembodiments where at least some physical design data are available forthe electronic circuit design, the electrical parasitics and/or physicalcharacteristics may be extracted or determined from the physical designdata. For example, the length of an interconnect may be directlyextracted from a layout including the routing information of theinterconnect. As another example, the length of an interconnect may alsobe determined or derived from a placement layout or a floorplanincluding no routing information by using the Manhattan distance betweenthe source and the destination of the interconnect.

The electrical parasitics may include electrical resistances,capacitances, inductances, etc. of various circuit components in theelectronic circuit design in some embodiments. These electricalparasitics may be extracted or determined by using, for example, thephysical characteristics of these circuit components in someembodiments. For example, the electrical resistance of an interconnectmay be determined by using the length of the interconnect, the width orprofile of the interconnect, and the resistivity of the interconnectmaterial, and optionally the temperature of the interconnect. In someother embodiments, the electrical parasitics may be obtained fromschematic level simulations (e.g., SPICE simulations) of the functionalcircuit.

At 210, the method or system may perform thermal, electrical, and/or EMCsimulation with the functional or electrical schematic view and thethermal schematic view by using one or more general purpose electroniccircuit simulators including, for example, one or more SPICE (SimulationProgram with Integrated Circuit Emphasis) or SPICE-like simulators,without using any time-stepping or discretization-based numericaltechniques such as finite element or finite difference methods in someembodiments. The thermal, EMC, and electrical analyses or simulationsmay be performed concurrently, in batch mode, or sequentially in someembodiments. The simulations of the electrical or functional view andthe thermal schematic view may be performed in parallel other oriteratively or sequentially while feeding simulation results to each ineither approach. In these embodiments, the method or system crosssimulates the electrical or function view and the thermal schematic viewand transmits simulation results between the electrical domain and thethermal domain to analyze the electronic circuit design in light ofdesign requirements of both the electrical or functional domain and thethermal domain.

At 212, the method or system may determine the steady-state and/ortransient thermal responses of the entire model or transient nodalresponses of the thermal schematic view as well as electrical responsesof the electrical or function view. The electrical view, the thermalschematic view, or both the electrical view and the thermal schematicview may be iteratively modified based at least in part upon thesimulation results until a convergence criterion or a stopping criterionis reached.

FIG. 2B illustrates a schematic flow diagram for data flows betweenanalysis modules for schematic driven, unified thermal andelectromagnetic interference compliance analyses for electronic circuitdesigns in some embodiments. More specifically, FIG. 2B illustrates theelectrical simulation or analysis modules 202B including, for example,the thermally-aware electrical simulation module 204B and thethermally-aware electromagnetic interference compliance (EMC) analysismodule 206B. The simulation or analysis modules 202B transmit electricalsimulation results (e.g., information or data about currents, voltages,etc.) to the thermal simulation module 208B using thermal schematic viewand one or more general purpose circuit simulators such as one or moreSPICE simulators or SPICE-like simulators.

The thermal simulation module 208B receives the thermal netlist or thethermal schematic view associated with thermal RC circuit network asinput and outputs steady-state and/or transient thermal responses of theentire model (e.g., the model for the entire thermal schematic view) orthe nodal thermal responses at various nodes in the thermal schematicview. The thermal simulation module 208B receives the electricalsimulation results from the electrical simulation or analysis module202B and use, for example, power dissipation for current sources and/orpin currents or interconnect segment currents (currents flowing throughinterconnect segments) as heat sources in the thermal schematic view. Insome embodiments, an interconnect may be modeled as an equivalentresistor for Joule heating by using the current (I) flowing through aswell as the resistance (R) of the interconnect to represent theinterconnect as a Joule heating source having the power of I²R.

In some of these embodiments, the interconnect may further be segmentedinto multiple segments (e.g., n segments, where n is a positive integergreater than 1) and modeled as n-Joule heating sources, each having thepower of I²R/n. In addition, depending on whether the physical designdata (e.g., placement data or routing data) are available, theresistance of an interconnect segment may be modeled by extracting thelength from the physical design data or by deriving the length fromManhattan distance between the source and destination of theinterconnect segment as described above. The Thermal simulation modulemay also transmit thermal simulation results to the electricalsimulation or analysis module 202B which then leverage the thermalsimulation results to fine tune the electrical or function view of theelectronic circuit design. For example, the temperature responses from208B may be transmitted to 202B so that the temperature-dependentelectrical resistances of circuit components may be adjusted using thetemperature responses.

FIG. 2C illustrates a more detailed block diagram for method or systemfor schematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.In these embodiments, the method or system may determine one or moreelectrical characteristics related to thermal behavior of one or morecircuit components of an electronic design in the first abstraction202C. In some of these embodiments, the electronic design in the firstabstraction comprises a schematic design including various schematic orstandard circuit component symbols and wire connections among thesecircuit component symbols without representing the physical arrangementor dimensions of these circuit component symbols or wire connections.

The one or more electrical characteristics may include, for example,power dissipation of a circuit component, pin currents, or currentsflowing through interconnect segments, etc. In some of theseembodiments, the one or more electrical characteristics may bedetermined from functional or schematic simulations such as simulationsusing SPICE or SPICE-like simulators. In some embodiments where theelectronic design includes analog devices, the functional or schematicsimulations may be carried out via SPICE or SPICE-like simulators. Insome embodiments where the electronic design includes mixed-signalcircuitry and/or digital circuitry, the method or system may replacedigital blocks of circuitry by respective input/output (I/O) models atthe respective I/O pins by using, for example, input/output bufferinformation specification (IBIS) models.

FIG. 2D shows some illustrative exchange of data for concurrent crossdomain analyses in some embodiments. In some of these embodiments, FIG.2D shows some illustrative exchange of data for concurrent electrical,electromagnetic interference compliance, and thermal analyses. Morespecifically, the method or system described herein may perform one ormore electrical simulations at 204D with the electrical or functionalschematic view 202D to generate electrical data 212D. The electricaldata may include initial electrical data including one or more initialconditions, boundary conditions, etc. in some embodiments.

In some other embodiments, the electrical data may include, for example,power dissipation of one or more devices, currents flowing through oneor more pins, pads, terminals, etc., currents flowing through one ormore interconnect segments, etc. at one or more intermediate stages ofthe electrical simulations 204D. In yet some other embodiments, theelectrical data generated may include, for example, the final convergentresults of power dissipation of one or more devices, currents flowingthrough one or more pins, pads, terminals, etc., currents flowingthrough one or more interconnect segments, etc. once the electricalsimulations 204D conclude.

In some embodiments, the electrical data may be further optionallyannotated, stitched, or associated with electrical parasitics from thelayout of the corresponding electronic design of interest. In otherwords, the electrical data 212D may be passed to the thermal analysismodule performing thermal analyses 210D on the thermal schematic view208D at any stage during or after the electrical simulation 204D. Thethermal analysis module may perform one or more thermal analyses at 210Don a thermal schematic view 208D with or without the electrical data byusing a general purpose circuit simulator such as a SPICE or SPICE-likesimulator to general thermal data 214D, without using any time-steppingor discretization based simulations such as the finite-elementtechniques or finite-difference techniques.

Upon or shortly after receiving electrical data 212D, the thermalanalysis module may perform the one or more thermal analyses with theelectrical data 212D to generate the thermal data 214D in light of theelectrical data 212D. The initial, intermediate, or finally convergentthermal data 214D may also be forwarded to the electrical simulator toperform one or more thermally-aware general circuit simulations 206D. Inthese embodiments illustrated in FIG. 2D, the electrical or functionalsimulations are thus thermally-aware; and the thermal simulations arethus electrically aware. In addition, the electrical simulations, thethermal simulations, and the EMC analyses may be performed concurrentlyor sequentially in these illustrated embodiments.

At 204C, a representation of the electronic design in the secondabstraction may be identified. The representation of an electronicdesign in the second abstraction may include, for example, a floorplan,a full or partial placement layout, or a full or partial routed design.At 206C, the method or system may extract the thermal RC circuit networkfor the electronic design in the first abstraction or in the secondabstraction. More details about thermal RC circuit extraction aredescribed in U.S. patent application Ser. No. 14/224,047, the content ofwhich is hereby expressly incorporated by reference in its entirety forall purposes. At 208C, the method or system may create the thermalcircuit view or representation for the electronic design in the firstabstraction using the thermal RC circuit network.

The thermal circuit view or representation may include, for example, athermal schematic view of the electronic circuit. In addition, thethermal circuit view or representation may be created by determining thethermal resistance (R_(TH)), the thermal capacitance (C_(TH)), and thepower or current sources (P) representing power dissipations of devicesfrom thermal RC circuit network extraction. In some of theseembodiments, the method or system may first identify or determine athermal response model in the frequency domain in response to a stepfunction input. The time constant or the lumped thermal resistance andthe lumped thermal capacitance for the thermal response model from, forexample, the results of electrical-thermal co-simulation. The thermalresponse of the thermal response model may be identified or determined,and the nodal thermal response of one or more nodes of interest may bedetermined with the thermal response. The thermal RC circuit may thus begenerated for a node of interest using the time constant or the thermalresistance and thermal capacitance. More details about extraction ofthermal RC circuits are described in U.S. patent application Ser. No.14/224,047 entitled “METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FORIMPLEMENTING THERMAL CIRCUIT EXTRACTION FOR TRANSIENT THERMAL ANALYSESFOR ELECTRONIC CIRCUIT DESIGNS” and filed on Mar. 24, 2014, the contentof which is hereby explicitly incorporated by reference in its entiretyfor all purposes.

At 210C, steady-state and/or transient thermal analyses may be performedwith the thermal circuit view or representation with one or more generalpurpose circuit simulators including, for example, one or more SPICE orSPICE-like simulators. In some embodiments, the steady-state and/ortransient thermal analyses are performed without using any time-steppingnumerical techniques such as finite element or finite difference methodsin some embodiments.

At 212C, the method or system may modify one or more thermal resistancevalue, one or more thermal capacitance values, or any combinationsthereof based at least in part upon the results of the steady-stateand/or transient thermal analyses. In some of these illustratedembodiments, the method or system may identify one or more criticalcomponents including those components whose thermal characteristics(e.g., thermal capacitances, thermal resistances, etc.) are abovecertain threshold percentage values (e.g., greater than or equal toninety percent) of permissible values. In these embodiments, the methodor system may adjust the thermal characteristics of these one or morecritical components to bring the thermal characteristics into a desiredor required range or level.

For example, if the method or system identifies an interconnect whoseJoule heating may have contributed more than a permissible level, themethod or system may shorten the interconnect to reduce the heatgeneration from Joule heating. In some of these embodiments, the methodmay modify a thermal resistance value of a thermal capacitance value ofa critical component at the expense of one or more other components. Inthe aforementioned example where the length of the interconnect isshortened, the method or system may move the component including thesource, the component including the destination, or both componentsincluding the source and destination of the interconnect to shorten thelength of interconnect, although such a modification may occur at theexpense increasing the corresponding lengths of one or more otherinterconnects connected to these moved component(s).

At 214C, the method or system may correlate the thermal resistancevalues and/or the thermal capacitances with their corresponding physicalimplementation constraints. For example, the method or system maycorrelate the thermal resistance value of an interconnect with thelength of the interconnect, given the width or profile of or associatedwith the interconnect. In these embodiments, the modified thermalresistance or capacitance values may be mapped to or correlated withphysical implementation constraints that may be driven or enforced inthe physical design or may be annotated onto or associated with thewiring connection in the corresponding electrical schematic design toupdate the physical design or the corresponding electrical schematicdesign. At 216C, the method or system may further optionally associatethe thermal analysis results (e.g., temperature) with the electronicdesign in the first abstraction.

For example, the temperature responses may be associated with orannotated onto the schematic design, the floorplan, or the placementlayout of the electronic circuit design. In these embodiments, thethermal analysis results may be incorporated when the method or systemfurther extracts or determines the electrical characteristics orparasitics from the electronic circuit design. For example, the methodor system may associate temperatures with the placement layout and usethe associated temperature to determine the temperature-dependentresistance values of interconnects. At 218C, the method or system mayimprove or optimize the electronic design in the first or the secondabstraction based at least in part upon the physical implementationconstraints. In the aforementioned example of reducing the thermalresistance value of an interconnect, the method or system effectivelyreduces the length of the interconnect by reducing, for example, thethermal resistance associated with the interconnect in the thermalschematic view.

The correlated length of the interconnect may thus be derived from thereduced thermal resistance value. The method or system may thus drive orenforce the correlated length in the electronic design in the first orthe second abstraction. For example, the method or system may move acomponent including the destination of the interconnect closer to theother component including the source of the interconnect in a floorplanor a placement layout such that the Manhattan distance is modifiedaccordingly. As another example, the method or system may annotate thecorrelated length of the interconnect with the wiring connection in aschematic view of the electronic design. The method or system mayiteratively return to 206C to perform another thermal RC circuit networkextraction in a substantially similar manner as previously described andthe proceed to 207C to perform verification of the electronic design inthe first abstraction level with the updated electronic design from218C.

FIG. 3 illustrates a high-level block diagram for a method or system forschematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.In these embodiments, the method or system may identify an electroniccircuit design at 302. In some of these embodiments, the thermal RCcircuit network of the electronic circuit design may also be extractedand associated with, for example, a schematic representation of theelectronic design to for a thermal schematic view. For example, themethod or system may create the thermal schematic view by determiningthe thermal resistance (R_(TH)), the thermal capacitance (C_(TH)), andthe power or current sources (P) representing power dissipations ofdevices from thermal RC circuit network extraction in identical orsubstantially similar manners as those described above for referencenumeral 208C.

In these embodiments illustrated in FIG. 3, the techniques andmethodologies described do not necessarily require the thermal RCcircuit network to enjoy the full functionality and achieve the fulleffects. In addition, the electronic design may include a schematicdesign, a floorplan, or a placement design of an IC design, an ICpackaging design, or a test bench design. At 304, the method or systemmay determine one or more electrical and/or physical characteristics forone or more interconnect models in the electronic design. In some ofthese embodiments, the one or more interconnect models may include oneor more parameterized models having at least one parameter for modelingor approximating one or more interconnects.

For example, a parameterized interconnect may include the lengthparameter, the width or cross-sectional area parameter, and atemperature parameter, each of which receives a parameter value to modelor approximate one or more interconnects in the electronic design. At306, the method or system may associate a schematic list with the one ormore electrical and/or physical characteristics for one or moreinterconnect models. These one or more interconnect models may be usedto, for example, model the Joule heating phenomenon of theseinterconnects represented with these one or more interconnected modelsin some embodiments.

At 308, the method or system may perform functional or electricalsimulation to determine the electrical characteristics (e.g., pincurrents, currents flowing through interconnect segments, nodalvoltages, power consumption, etc.) In some of these embodiments, thefunctional or electrical simulation may be performed in conjunction withone or more steady-state or transient thermal analyses to cross simulateboth the electrical behavior and the thermal responses of the electroniccircuit design. At 310, the method or system may determine theelectromagnetic interference compliance (EMC) based at least in partupon the results of the electrical or functional simulation performed at308. For example, the method or system may determine whether thesimulated harmonic content of a circuit component is greater than apredetermined threshold (e.g., a threshold percentage) with respect to apermissible value to determine whether the circuit component raises EMCconcerns.

FIG. 3A illustrates a more detailed block diagram for a method or systemfor schematic driven, unified thermal and electromagnetic interferencecompliance analyses for electronic circuit designs in some embodiments.In these embodiments illustrated in FIG. 3A, the method or system mayperform circuit simulation on a functional circuit of an electronicdesign. In some of these embodiments illustrated in FIG. 3A, the circuitsimulation includes one or more schematic level simulations thatdetermine harmonic content of circuit components by using Fouriertransforms of switching current and voltage waveforms. In addition or inthe alternative, the electronic design includes an integrated circuit(IC) design, an IC packaging design including an IC design, a PCB(printed circuit board) design including one or more IC packagingdesigns, and a test bench design including the PCB design in someembodiments.

At 304A, the method or system may optionally identify or create afloorplan, a partial or full placement layout, or a partially or fullyrouted layout. One or more interconnect models may be identified (ifexisting) or determined (if not existing) at 306A. In some of theseembodiments illustrated in FIG. 3A, the one or more interconnect modelsmay be based at least in part upon the physical design data of theoptionally identified or created floorplan, the partial or fullplacement layout, or the partially or fully routed layout. For example,the method or system may extract the geometric characteristics (e.g.,length and width or profile of an interconnect) of the interconnectsfrom a partially or fully routed layout to create the one or moreinterconnect models. As another example, the method or system maydetermine the geometric characteristics of an interconnect for aninterconnect model by using, for example, the Manhattan distance betweenthe source and the destination of the interconnect and the widthassociated with the interconnect.

An interconnect model of these one or more interconnect models mayinclude the temperature-dependent characteristics such as electricalresistance in some embodiments. In some embodiments, one or more ofthese physical or electrical characteristics may be represented in aparameter form awaiting their respective input values to model aparticular interconnect. For example, an interconnect model may includea first parameter for the length, a second parameter for the width, anda third parameter for the temperature of the interconnect. Uponreceiving the respective length, width, and temperature values, themethod or system may use these received values to model a particularinterconnect. At 308A, one or more electrical simulations may beperformed on the electronic circuit with the one or more interconnectmodels identified or determined at 306A.

The one or more electrical simulations may be performed on a generalpurpose circuit simulator such as a SPICE or SPICE-like simulator. Themethod or system may then check the simulation results forelectromagnetic interference compliance (EMC) or other applicableanalyses at 310A. In some of these embodiments, the method or system maycheck the simulation results after a convergence criterion or a stoppingcriterion (e.g., a threshold number of iterations has been reached, thevariations between a successive number of iterations fall within a rangeor below a threshold value, etc.) Upon identifying one or more EMCissues (e.g., the simulated harmonic content exceeds a thresholdpercentage such as ninety percent of the permissible value) orviolations (e.g., the simulated harmonic content exceeds the permissiblevalue), the method or system may modify one or more values of thecorresponding one or more parameters of an interconnect model based atleast in part upon the results of checking the simulation forelectromagnetic interference compliance at 312A.

For example, the method or system may modify the length value of aninterconnect to resolve the EMC issue or violation. The functionalcircuit design, floorplan, or layout may be modified accordingly at 314Abased at least in part upon the one or more modified values of the oneor more parameters. For example, the method or system may annotate,stitch or associate the modified value with the schematic design in someembodiments where the electronic design under consideration is theschematic. As another example, the method or system may update theplacement layout to reflect the modified length value of theinterconnect such that the Manhattan distance between the source anddestination of the interconnect corresponds to the modified lengthvalue.

As yet another example, the method or system may invoke the routingengine to re-route or modify the interconnect of a partially or fullyrouted layout to reflect the modified length value of the interconnect.At 316A, the method or system may then extract or determine theelectrical characteristics from the modified schematic, floorplan, orlayout and update one or more interconnect models based at least in partupon the extracted electrical characteristics at 318A. For example, themethod or system may perform one or more simulations on the electricalschematic of the electronic circuit to obtain the updated pin currents,the currents flowing through interconnect segments based on the pincurrents, the power dissipation of one or more interconnects, etc. at316A and update the corresponding interconnect models in the electronicdesign. With the electronic design including the one or more updatedinterconnect models, the method or system may return to 306A oroptionally return to 304A and repeat the acts described above until anelectromagnetic interference compliant electronic design is achieved oruntil a stopping criterion is met (e.g., simulation results showingcritical devices as electromagnetic interference compliant).

FIG. 3B illustrates another more detailed block diagram for a method orsystem for schematic driven, unified thermal and electromagneticinterference compliance analyses for electronic circuit designs in someembodiments. More specifically, FIG. 3B illustrates the embodiments ofunified electrical analysis, thermal analysis, and EMC analysis for apre-layout electronic design. In these embodiments illustrated in FIG.3B, the method or system may identify an electronic design capturing afunction circuit at 302B. The electronic design may include anyrepresentation of the electronic design in a pre-layout stage that isprior to the completion of the placement process. At 304B, the method orsystem may optionally generate a floorplan or a preliminary placementdesign for which the placement is not completed.

The thermal RC circuit network may be extracted at 306B by using varioustechniques described in U.S. patent application Ser. No. 14/224,047,which is expressly incorporated by reference in its entirety for allpurposes. In some embodiments, the method or system may overlay theextracted thermal RC circuit of each device on the corresponding devicein the functional or electrical schematic view to form the thermalschematic view. In some embodiments, the method or system may create thethermal schematic view by determining the thermal resistance (R_(TH)),the thermal capacitance (C_(TH)), and the power or current sources (P)representing power dissipations of devices from thermal RC circuitnetwork extraction to form the thermal schematic view in identical orsubstantially similar manners as those described for reference numeral208C.

The method or system may further determine one or more electricalcharacteristics, one or more physical characteristics, or anycombinations thereof for at least one interconnect in the electronicdesign at 308B. Because the electronic design is at the pre-layout stageand thus includes no routing information, the method or system maydetermine, for example, the approximate length of an interconnect byusing the Manhattan distance between the source and the destination ofthe interconnect. The method or system may also use the width value forthe interconnect to be subsequently added to the electronic design asthe approximate width of the interconnect. In addition, the method orsystem may consult the technology file or library including thethickness of a metal layer to which the interconnect belongs to identifythe approximate thickness of the interconnect.

The method or system may further use these approximate physicalcharacteristics together with, for example, the bulk resistivity of theinterconnect material to determine the electrical resistance (R) of theinterconnect at 308B. In some embodiments where the functional orelectrical simulation results have been identified, the method or systemmay further use the current (I) flowing through the interconnect todetermining the Joule heating for the interconnect. This interconnectmay then be modeled as a heat source generating I²R as the amount ofJoule heating released or dissipated by the interconnect.

In some embodiments, the method or system may further segment theinterconnect into multiple interconnect segments (e.g., n segments,where n is a positive integer greater than one). This interconnect maythus be modeled as “n” different heat sources distributed along theinterconnect path, and each of these “n” heat sources generates I²R/n asthe amount of Joule heating released or dissipated by the interconnectsegment. In some embodiments, the one or more electrical characteristicsmay include the inductance (e.g., self-inductance or mutual inductance)associated with the interconnect by using the length value and theelectric current information (e.g., the time rate of change of theelectric current through the interconnect). In some of theseembodiments, an interconnect may be modeled as a parameterized modelthat receives one or more parameter values (e.g., length, width,thickness, cross-sectional area, temperature, electric current, timerate of change of electric current, etc.) for defining a specificinterconnect.

These one or more electrical and/or physical characteristics may bestitched onto, annotated in, or associated with the electronic design at310B. For example, the method or system may stitch, annotate, orassociate the one or more electrical characteristics and/or one or morephysical characteristics with a schematic netlist of the electronicdesign at 310B. At 312B, the method or system may further identify oneor more properties (e.g., thermal conductivity of the material, heattransfer coefficient of a medium, etc.), and/or one or more conditions(e.g., one or more boundary conditions, one or more initial conditions,or any combinations thereof, etc.) that may be needed for thermalanalyses.

At 314B, the method or system may iterative perform thermally-awarefunctional or electrical simulation in which the electrical simulationof the functional or schematic circuit and the thermal simulation usingthe extracted thermal RC circuit network are iteratively performed ineach other's context to transmit respective simulation results to eachother. For example, the electric current information from electricalsimulations may be forwarded to thermal simulations to more correctlycapture the thermal effects of Joule heating and power dissipation ofdevices. As another example, the temperature responses from the thermalsimulations may also be forwarded to the electrical simulations to moreaccurately model the temperature-dependent properties (e.g., electricalresistance) of materials. The thermally-aware functional or electricalsimulation and the electrically-aware thermal simulation may beiterative performed until a convergence criterion or a stoppingcriterion is reached.

At 316B, the method or system may perform the thermally-aware EMCanalysis by at least checking the simulation results for electromagneticinterference (EMI) compliance. In the event that an EMC issue or an EMCviolation is detected, the method or system may modify the preliminaryplacement design or the floorplan based at least in part upon theresults of the thermally-aware EMC analysis at 318B in substantiallysimilar manners as those described for 314A. The method or system mayreturn to 306B and repeat the aforementioned acts from 306B until anelectromagnetic interference compliant electronic design is achieved oruntil a stopping criterion (a prescribed threshold amount of iterationtime, a threshold number of iterations, the total number of EMC issuesand/or EMC violations, etc.) is reached. In some of these illustratedembodiments where the floorplan or the partially placed design ismodified at 318B, the method or system may further verify thecorrectness of the electronic design after the modifications at 318B. At320B, the method or system may identify one or more EMC criticalcomponents based at least in part upon the results of thethermally-aware EMC analysis. In some embodiments, the one or more EMCcritical components may also be identified as such or may be identifiedwith different identifiers (e.g., different color coding) to indicatethe severity of the EMI issue or EMI violation.

FIG. 4 illustrates a high level block diagram for a process or modulefor performing schematic driven thermal analyses accounting for deviceheat dissipation and interconnect Joule heating for electronic circuitdesigns in some embodiments. In these embodiments illustrated in FIG. 4,the method or system may identify, determine, or estimate one or morecharacteristics one or more circuit components of an electronic circuitdesign from functional or electrical simulation results of theelectronic circuit design at 402. The one or more characteristics mayinclude, for example, electric current information including average,peak, or transient electric currents at various pins, pads, terminals,or ports (collectively “pin currents”), electric currents flowingthrough various interconnect segments, power dissipation of one or moredevices, etc. from the electrical or functional simulation results.

In some of these embodiments illustrated in FIG. 4, the functional orelectrical simulation includes one or more simulations at theinput/output (I/O) level using IBIS models on an IBIS simulator toobtain worst case or corner case scenarios. These embodiments remove theneed for an HDL (hardware description language) model for the electroniccircuit designs. At 404, the method or system may associate the one ormore characteristics with one or more representations of the electronicdesign in one or more corresponding abstraction levels. The one or morerepresentations may include, for example, a floorplan, a full or partialplacement layout, a fully or partially routed layout, or an IBIS modelsuitable for IBIS simulations of the electronic design in someembodiments.

At 406, the method or system may determine the thermal effects orresponses of the one or more circuit components in the electronic designusing the one or more characteristics identified, determined, orestimated at 402. In some of these embodiments, the method or system mayuse the one or more characteristics such as the current informationand/or power dissipation in the thermal simulation or analysis todetermine the thermal responses or effects. For example, the method orsystem may use the pin currents or the interconnect segment electriccurrents to model the Joule heating effects of interconnects orinterconnect segments. In some embodiments, the method or system mayfurther segment an interconnect into multiple interconnect segments(e.g., n segments, where n is a positive integer greater than one). Thisinterconnect may thus be modeled as “n” different heat sourcesdistributed along the interconnect path, and each of these “n” heatsources generates I²R/n as the amount of Joule heating released ordissipated by the interconnect segment for the thermal simulation oranalysis.

At 408, the method or system may perform thermal simulation or analysisusing at least the thermal effects or responses determined at 406. Forexample, the method or system may use the power dissipation of a deviceas a heat generation source for a device and the Joule heating effectsas another heat generation source for an interconnect or a segmentthereof and perform the thermal simulation or thermal analysis using anIBIS simulator. In some other embodiments, the method or system may useother simulation techniques other than using an IBIS simulator toperform thermal simulation or analysis. For example, the method orsystem may use a brute force approach to simulate a transistor model ofthe electronic design or various other die-level, IC-package level, orPCB-level thermal models.

FIG. 5 illustrates a more detailed block diagram of a process or modulefor performing schematic driven thermal analyses accounting for deviceheat dissipation and interconnect Joule heating for electronic circuitdesigns in some embodiments. In these embodiments illustrated in FIG. 5,the method or system may identify or extract a thermal RC circuitnetwork for a thermal schematic view of an electronic design. In some ofthese illustrated embodiments, the thermal schematic view may beassociated, annotated, or stitched with electric information including,for example, power dissipation of one or more devices, electric currents(e.g., average currents, root-mean square (RMS) or quadratic meancurrents, average currents, transient current waveforms, etc.), variouselectric parasitics (e.g., electrical resistances, capacitances,inductances, etc.) of one or more circuit design components, physicalcharacteristics of one or more circuit design components (e.g., thelength, width, or profile of a circuit component, the resistivity of thematerial of a circuit component, or the temperature of a circuitcomponent, etc.), or any other suitable information.

At 502, the thermal RC circuits may be identified for a thermalschematic view of an electronic design. The method or system mayidentify or determine one or more first characteristics of one or morecircuit components at 504. The one or more first characteristics mayinclude, for example, the electrical resistance of an interconnect insome embodiments. In some embodiments described in this application, themethod or system may identify a piece of information or data if thatpiece of information or data already exists. On the other hand, themethod or system may determine the piece of information or data if thatpiece of information or data does not exist at the time the method orsystem is to identify the piece of information or data. In these latterembodiments, the method or system may determine such piece ofinformation or data by performing various processes or acts (e.g.,analysis, computation, etc.)

The method or system may also optionally subdivide at least one of theone or more first circuit components into the corresponding multiplesub-components at 506. For example, the method or system may sub-dividean interconnect or a segment thereof into multiple, smaller sub-segmentsat 506. In these embodiments where a circuit component is sub-dividedinto multiple sub-components, each of these multiple sub-components maybe individually modeled in the thermal schematic view. For example, aninterconnect segment may be modeled as a single Joule heating source byusing, for example, the length, the bulk electrical resistivity, and theprofile or width to model the interconnect segment as a resistor in athermal schematic view of a circuit design in some embodiments. In someother embodiments, the interconnect segment may be sub-divided intomultiple, smaller segments.

Each of these multiple, smaller segments may be individually modeled asa resistor with, for example, the length and the width or profile of theinterconnect and the bulk resistivity of the interconnect material inthe thermal schematic view. At 508, the method or system may furtheridentify, determine, or estimate one or more second characteristics ofone or more corresponding second circuit components or of the multiple,sub-components from simulation results of the electronic circuit design.In some of these embodiments, the one or more second characteristics mayinclude electric currents flowing into or out of one or more pins, pads,or terminals, or power dissipation of the one or more second circuitcomponents based on the electric current information, etc. Thesimulation results may include the results of one or more electricalsimulations on the electronic design at the schematic or functionallevel in some embodiments. Based at least in part upon these one or moresecond characteristics, the method or system may determine one or morefirst electrical characteristics of the one or more circuit componentsor the multiple sub-components, if available, at 510. The one or morefirst electrical characteristics may include, for example, electriccurrents flowing from various pins, terminals, or pads through one ormore interconnect segments in some embodiments.

At 512, the method or system may perform one or more thermal analyses orsimulations by using the one or more thermal RC circuits of the thermalschematic view to obtain the thermal responses for the electroniccircuit design. In some embodiments, the method or system may use aSPICE or a SPICE-like simulator for the one or more thermal analyses orsimulations. In addition or in the alternative, the method or system mayuse the one or more first characteristics and/or the one or more secondcharacteristics in the thermal analyses or simulations. For example, themethod or system may use the a parameterized interconnect model to modelthe Joule heating effects of interconnect segments.

The parameterized interconnect model may include one or more parametersthat receive one or more corresponding values of, for example, thelength information, the width, profile, or cross-sectional are, the bulkresistivity of the material, electric current, and/or the temperature(“T”) information to model an interconnect segment. The parameterizedmodel may then model the Joule heating effects of various interconnectsegments by using the respective values of these interconnect segmentsby using the Joule's first law. At 514, the method or system may adjustat least one of the one or more first characteristics based at least inpart upon the thermal responses of the electronic design. The method orsystem may then return to 404B to identify the updated one or more firstcharacteristics and repeat the acts as describe above until aconvergence or stopping criterion is reached. For example, the methodmay determine from the thermal response that an interconnect segment maygenerate an excessive amount of heat from Joule's heating at 512.

The method or system may attempt to reduce the excessive amount of heatgeneration or dissipation due by reducing the electrical resistance ofthe interconnect in the thermal schematic view at 514. This reducedlength translates to the change in the length of the interconnect. Themethod or system may thus adjust the electronic design accordingly by,for example, changing the placement of the source component ordestination component of the interconnect to change the Manhattandistance for the interconnect (where routing information isunavailable), changing the route of the interconnect (where routinginformation is available), or changing the length information associatedwith the thermal schematic view or the electrical schematic view of theelectronic design.

FIG. 6 illustrates a portion of a user interface for the schematicdriven concurrent EMC, thermal, and electrical simulations techniquesdescribed above in some embodiments. The thermal RC circuits may beextracted and imported into or associate with the electrical model toform a thermal schematic view that has exactly the same circuit nodes asthe electrical schematic. In this manner, the thermal schematic view mayalso be simulated with a schematic level simulator such as a SPICE orSPICE-like simulator, without having to use the conventionaltime-stepping or discretization-based numerical techniques for transientand steady-state thermal analyses or simulations. It shall be noted thatvarious methods or system described herein may perform the EMC analyses,the thermal analyses or simulations, and the electrical simulations oranalyses concurrently, although the concurrent performance of thesethree types of analyses or simulations does not preclude the possibilityof running these analyses or simulations in a batch mode orsequentially.

FIG. 7 shows a portion of a user interface illustrating a functional orelectrical simulation view for a method or system for schematic driven,unified thermal and electromagnetic interference compliance analyses forelectronic circuit designs in some embodiments. As described above, themethod or system may update the thermal schematic view for to reflectchanges in the placement layout or routed layout. Similarly, the methodor system may also update the placement layout or routed layout toreflect any changes in the thermal schematic view. For example, anelectrical resistance value of an interconnect may be altered in athermal schematic view based on some thermal analysis results to reducethe Joule heating effect of the interconnect.

Upon or shortly after the change in the electrical resistance, themethod or system may change, for example, the source component and/orthe destination component in the placement layout for the interconnectto reflect the reduced electrical resistance that corresponds to ashorter length and hence a shorter Manhattan distance between the sourcecomponent and the destination component in the placement layout. If arouted layout for the portion including the interconnect is alsoavailable, the method or system may also invoke the router to change therouted design of the interconnect to reflect the reduced length from thereduced electrical resistance. In some embodiments where the electricalor thermal schematic view is also stitched with or associated with theinterconnect length information, the method or system may also changethe stitched or associated length information in the electrical orthermal schematic view.

Similar changes may also be propagated from the layout or electricalschematic to the thermal schematic view. That is, if the position orlength of an interconnect is altered in a layout (either the actuallength from a routed design or the Manhattan distance from a placementlayout), the corresponding electrical resistance and/or thermalresistance (from thermal RC extraction) in the thermal schematic viewmay also be updated to reflect the change.

FIG. 8 shows a portion of a thermal schematic view and a portion of anelectrical schematic view of an electronic circuit design in someembodiments. More specifically, a thermal schematic view 806 includingthe thermal schematic portion 808 may be constructed from thecorresponding electrical schematic portion 804 in an electricalschematic view 802 using the thermal resistances (R_(TH)), thermalcapacitances (C_(TH)), and the power or current sources (P_(TH)) viathermal RC circuit extraction as described above.

FIG. 9 illustrates a portion of a user interface for performing athermal simulation or analysis for an electronic circuit in someembodiments. More specifically, FIG. 9 illustrates a portion of the userinterface for performing thermal simulation or analysis with a thermalschematic view 806 of FIG. 8 that may be determined from thecorresponding electrical schematic view of the electronic circuit. Thethermal schematic view of the electronic circuit includes the thermalresistances (R_(TH)), thermal capacitances (C_(TH)), and the power orcurrent sources (P_(TH)) that are extracted from the electronic circuitdesign and imported into or overlaid onto the electrical schematic viewhaving the same circuit nodes in substantially similar or identicalmanners as described above. The user interface also provides the optionsfor the designer to use general purpose electronic circuit simulatorsinclude SPICE or SPICE-like simulation engines to perform thermalanalyses or simulations. The user interface may also display theelectrical schematic view and the thermal schematic view in a cascade,tiled, or split-window manner such that the designer may refer to bothviews in light of the EMC, thermal, and/or electrical simulation oranalysis results.

FIG. 10 illustrates tabulated electrical-thermal-EMC co-simulationresults including graphical indications of criticality of components ofan electronic design with respect to electromagnetic interferencecompliance in some embodiments. In these illustrated embodiments, theco-simulation results may include the numerical values of the simulatedresults (e.g., the simulated peak, RMS, average currents of variouscomponents, the corresponding deratings of various components, etc.).The co-simulation results may also include graphical representations ofthese simulated results with respect to the corresponding deratings. Insome embodiments, the simulated results may be identified with visualindicators for different categories of results.

For example, some textual or graphical information or data 1002 in thesimulation results may be represented in a yellow color to indicate thatthe textual or graphical information or data is, for example, within apredetermined threshold percentage of the permissible level (e.g., 90%of the derating of the circuit component). Some textual or graphicalinformation or data 1004 in the simulation results may be represented ina red color to indicate that the textual or graphical information ordata exceeds a predetermined threshold permissible level (e.g.,exceeding the derating of the circuit component). Moreover, thesimulation results may also include or compute the time derivatives ofthe currents, voltages, or temperatures (e.g., dl/dt, dV/dt, or dT/dtwhere I stands for electric current, V stands for voltage, and T standsfor temperature) to determine whether certain devices raise EMC issues,electrical issues, or thermal issues to identify certain devices as EMC,electrically, or thermally critical devices. In some embodiments, thesimulation results may also use graphical and/or textual indicators toemphasize these critical devices in the user interface.

FIG. 11 illustrates a portion of a user interface including a thermalschematic view 1102 and the corresponding placement layout 1104 of anelectronic circuit design or a portion thereof for cross-editing in someembodiments. The thermal schematic view 1102 and the correspondingplacement layout 1104 may be presented in a single user interface or intwo separate user interfaces of a two separate electronic designautomation tools (e.g., a schematic editor and a placement tool). Inaddition, a design may initiate a change in one of the views (e.g., inthe thermal schematic view 1102), and the method or system describedherein may automatically update the other view with the correspondingchange.

FIG. 12 illustrates a layout view or a portion thereof including analog,digital, mixed-signal components, and interconnects with associated orstitched schematic level electrical characteristics in some embodiments.In some embodiments, the method or system may pass electricalinformation obtained at the schematic level to the corresponding layoutportion. The electrical information may be obtained from, for example,schematic or electrical simulations with a SPICE or SPICE-like simulatoron an electrical schematic view of the layout and may include, forexample, electric currents at pins, pads, or terminals and powerdissipation of devices.

FIG. 13 illustrates an electric schematic view or a portion thereofincluding associated, stitched, or annotated electrical and thermal datafrom layout-based analyses in some embodiments. In some embodiments, themethod or system may annotate the schematic view with thermal responsesor data from thermal analysis on a thermal schematic view. Theelectronic design to which various techniques or methodologies apply mayinclude a test bench design including a printed circuit board (PCB)design and various components (e.g., interconnects and devices) at thetest bench level, a PCB design including one or more IC (integratedcircuit) packaging designs, interconnects, and circuit components at thePCB level, and an IC packaging design including a die, interconnects,and IC packaging.

System Architecture Overview

FIG. 14 illustrates a block diagram of an illustrative computing system1400 suitable for implementing pulse-density modulation audiointellectual property block as described in the preceding paragraphswith reference to various figures. Computer system 1400 includes a bus1406 or other communication mechanism for communicating information,which interconnects subsystems and devices, such as processor 1407,system memory 1408 (e.g., RAM), static storage device 1409 (e.g., ROM),disk drive 1410 (e.g., magnetic or optical), communication interface1414 (e.g., modem or Ethernet card), display 1411 (e.g., CRT or LCD),input device 1412 (e.g., keyboard), and cursor control (not shown).

According to one embodiment, computer system 1400 performs specificoperations by one or more processor or processor cores 1407 executingone or more sequences of one or more instructions contained in systemmemory 1408. Such instructions may be read into system memory 1408 fromanother computer readable/usable storage medium, such as static storagedevice 1409 or disk drive 1410. In alternative embodiments, hard-wiredcircuitry may be used in place of or in combination with softwareinstructions to implement the invention. Thus, embodiments of theinvention are not limited to any specific combination of hardwarecircuitry and/or software. In one embodiment, the term “logic” shallmean any combination of software or hardware that is used to implementall or part of the invention.

Various actions or processes as described in the preceding paragraphsmay be performed by using one or more processors, one or more processorcores, or combination thereof 1407, where the one or more processors,one or more processor cores, or combination thereof executes one or morethreads. For example, the act of specifying various net or terminal setsor the act or module of performing verification or simulation, etc. maybe performed by one or more processors, one or more processor cores, orcombination thereof. In one embodiment, the parasitic extraction,current solving, current density computation and current or currentdensity verification is done in memory as layout objects or nets arecreated or modified.

The term “computer readable storage medium” or “computer usable storagemedium” as used herein refers to any medium that participates inproviding instructions to processor 1407 for execution. Such a mediummay take many forms, including but not limited to, non-volatile mediaand volatile media. Non-volatile media includes, for example, optical ormagnetic disks, such as disk drive 1410. Volatile media includes dynamicmemory, such as system memory 1408. Common forms of computer readablestorage media includes, for example, electromechanical disk drives (suchas a floppy disk, a flexible disk, or a hard disk), a flash-based,RAM-based (such as SRAM, DRAM, SDRAM, DDR, MRAM, etc.), or any othersolid-state drives (SSD), magnetic tape, any other magnetic ormagneto-optical medium, CD-ROM, any other optical medium, any otherphysical medium with patterns of holes, RAM, PROM, EPROM, FLASH-EPROM,any other memory chip or cartridge, or any other medium from which acomputer can read.

In an embodiment of the invention, execution of the sequences ofinstructions to practice the invention is performed by a single computersystem 1400. According to other embodiments of the invention, two ormore computer systems 1400 coupled by communication link 1415 (e.g.,LAN, PTSN, or wireless network) may perform the sequence of instructionsrequired to practice the invention in coordination with one another.

Computer system 1400 may transmit and receive messages, data, andinstructions, including program, i.e., application code, throughcommunication link 1415 and communication interface 1414. Receivedprogram code may be executed by processor 1407 as it is received, and/orstored in disk drive 1410, or other non-volatile storage for laterexecution. In an embodiment, the computer system 1400 operates inconjunction with a data storage system 1431, e.g., a data storage system1431 that includes a database 1432 that is readily accessible by thecomputer system 1400. The computer system 1400 communicates with thedata storage system 1431 through a data interface 1433. A data interface1433, which is coupled to the bus 1406, transmits and receiveselectrical, electromagnetic or optical signals that include data streamsrepresenting various types of signal information, e.g., instructions,messages and data. In embodiments of the invention, the functions of thedata interface 1433 may be performed by the communication interface1414.

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention. Forexample, the above-described process flows are described with referenceto a particular ordering of process actions. However, the ordering ofmany of the described process actions may be changed without affectingthe scope or operation of the invention. The specification and drawingsare, accordingly, to be regarded in an illustrative rather thanrestrictive sense.

We claim:
 1. A computer implemented method for schematic driven, unifiedthermal and electromagnetic interference compliance analyses forelectronic circuit designs, comprising executing a sequence ofinstructions by using at least one processor or processor core executingone or more threads of the computing system to perform a process, theprocess computing: identifying or generating a representation of anelectronic design; generating a thermal representation of the electronicdesign by associating thermal RC circuits of the electronic design withthe representation; and performing at least two analyses of anelectrical analysis, a thermal analysis, and an electromagneticinterference compliance (EMC) analysis with the representation and thethermal representation of the electronic design.
 2. The computerimplemented method of claim 1, the process further comprising:extracting the thermal RC circuits for the electronic design, whereinthe representation comprises an electrical schematic of the electronicdesign, and the thermal representation comprises a thermal schematicincluding same nodes as the electrical schematic.
 3. The computerimplemented method of claim 1, the act of generating the thermalrepresentation further comprising: identifying the thermal RC circuitsof the electronic design; identifying corresponding electrical circuitcomponents that correspond to the thermal RC circuits in therepresentation of the electronic design; and forming the thermalrepresentation by at least importing the thermal RC circuits into therepresentation according to the corresponding electrical circuitcomponents in the representation.
 4. The computer implemented method ofclaim 1, the process further comprising at least one of: associating oneor more electrical characteristics and/or one or more physicalcharacteristics with the representation and/or the thermalrepresentation of the electronic design; stitching the one or moreelectrical characteristics and/or the one or more physicalcharacteristics into the representation and/or the thermalrepresentation of the electronic design; and annotating one or moreelectrical characteristics and/or one or more physical characteristicsonto the representation and/or the thermal representation of theelectronic design.
 5. The computer implemented method of claim 1,wherein the thermal analysis is performed by using at least one generalpurpose circuit simulator including a SPICE (Simulation Program withIntegrated Circuit Emphasis) or SPICE-like simulation engine.
 6. Thecomputer implemented method of claim 1, the process further comprisingat least one of: determining steady-state thermal responses of theelectronic design by using the results; and determining transientthermal responses of the electronic design by using the results.
 7. Thecomputer implemented method of claim 1, the process further comprising:forwarding thermal analysis results to the electrical analysis or theEMC analysis; and performing the electrical analysis or the EMC analysiswith at least the thermal analysis results to obtain electrical analysisresults or EMC analysis results.
 8. The computer implemented method ofclaim 7, the process further comprising: forwarding the electricalanalysis results or the EMC analysis results to the thermal analysis;and performing the thermal analysis with at least the electricalanalysis results or the EMC analysis results to obtain updated thermalanalysis results until a criterion is satisfied.
 9. The computerimplemented method of claim 1, the process further comprising:performing an electrical simulation on the representation of theelectronic design to obtain one or more electrical characteristics ofthe electronic design, wherein the one or more electricalcharacteristics include one or more pin currents and power dissipationof one or more devices.
 10. The computer implemented method of claim 1,the process further comprising: modifying one or more firstcharacteristics of the thermal representation of the electronic designbased at least in part upon the results; and automatically modifying oneor more second characteristics of the representation or a layout portionof the electronic design according to the one or more firstcharacteristics that are modified.
 11. The computer implemented methodof claim 10, the process further comprising: modifying the one or moresecond characteristics of the representation or the layout portion ofthe electronic design based at least in part upon the results; andautomatically modifying the one or more first characteristics of thethermal representation of the electronic design according to the one ormore second characteristics that are modified.
 12. The computerimplemented method of claim 10, wherein the one or more firstcharacteristics include at least a size of a circuit component design,and the one or more second characteristics include at least a thermalresistance of the circuit component design.
 13. The computer implementedmethod of claim 1, wherein the electronic design is at a pre-layoutstage having no placement or routing design information.
 14. Thecomputer implemented method of claim 1, the process further comprisingat least one of: identifying electrical characteristics from therepresentation of the electronic design and forwarding the electricalcharacteristics to the thermal representation of the electronic designfor the thermal analysis; sub-dividing a circuit component design intomultiple sub-component designs and performing the at least two analyseswith the multiple sub-component designs; and identifying one or more EMCcritical components in the electronic design based at least in part uponthe results.
 15. A system for schematic driven, unified thermal andelectromagnetic interference compliance analyses for electronic circuitdesigns, comprising: non-transitory computer readable storage memorystoring thereupon program code, the program code comprising a sequenceof instructions; a process or a processor core executing one or morethreads in a computing system to execute the sequence of instructions ofthe program code to: identify or generate a representation of anelectronic design; generate a thermal representation of the electronicdesign by associating thermal RC circuits of the electronic design withthe representation; perform at least two analyses of an electricalanalysis, a thermal analysis, and an electromagnetic interferencecompliance (EMC) analysis with the representation and the thermalrepresentation of the electronic design; and store results of performingthe at least two analyses.
 16. The system of claim 15, wherein theprocessor or processor core further executes the sequence ofinstructions of the program code to: extract the thermal RC circuits forthe electronic design, wherein the representation comprises anelectrical schematic of the electronic design, and the thermalrepresentation comprises a thermal schematic including same nodes as theelectrical schematic.
 17. The system of claim 15, wherein the processoror processor core further executes the sequence of instructions of theprogram code to: identify the thermal RC circuits of the electronicdesign; identify corresponding electrical circuit components thatcorrespond to the thermal RC circuits in the representation of theelectronic design; and form the thermal representation by at leastimporting the thermal RC circuits into the representation according tothe corresponding electrical circuit components in the representation,wherein the representation comprises an electrical schematic of theelectronic design, and the thermal representation comprises a thermalschematic including same nodes as the electrical schematic.
 18. Anarticle of manufacture comprising a non-transitory computer accessiblestorage medium having stored thereupon a sequence of instructions which,when executed by at least one customizable processor executing one ormore threads, causes the at least one customizable processor to performa method for schematic driven, unified thermal and electromagneticinterference compliance analyses for electronic circuit designs, themethod comprising: identifying or generating a representation of anelectronic design; generating a thermal representation of the electronicdesign by associating thermal RC circuits of the electronic design withthe representation; performing at least two analyses of an electricalanalysis, a thermal analysis, and an electromagnetic interferencecompliance (EMC) analysis with the representation and the thermalrepresentation of the electronic design; and storing results ofperforming the at least two analyses.
 19. The article of manufacture ofclaim 18, the method further comprising: extracting the thermal RCcircuits for the electronic design, wherein the representation comprisesan electrical schematic of the electronic design, and the thermalrepresentation comprises a thermal schematic including same nodes as theelectrical schematic.
 20. The article of manufacture of claim 18, themethod further comprising: identifying the thermal RC circuits of theelectronic design; identifying corresponding electrical circuitcomponents that correspond to the thermal RC circuits in therepresentation of the electronic design; and forming the thermalrepresentation by at least importing the thermal RC circuits into therepresentation according to the corresponding electrical circuitcomponents in the representation, wherein the representation comprisesan electrical schematic of the electronic design, and the thermalrepresentation comprises a thermal schematic including same nodes as theelectrical schematic.